1. Field of the Invention
The present invention relates to field-effect semiconductor devices, and more specifically, it relates to a field-effect semiconductor device having a heterojunction structure such as an HEMT structure or a DCHFET structure.
2. Description of the Related Art
Hitherto, as transistor devices operating in the region from microwaves to millimeter waves, a field-effect transistor having a heterojunction structure (hereinafter referred to as a heterojunction FET) has been used. In accordance with doped structures, the heterojunction FETs can be roughly classified into HEMTs (high-electron-mobility transistors) using a modulation-doped structure and DCHFETs (doped-channel heterojunction FETs) using a channel-doped structure. In this connection, the latter DCHFET is also called a DMT, an MISFET, an HIGFET, and the like.
FIG. 1 is a schematic cross-sectional view showing a semiconductor structure of a conventional HEMT. In an HEMT 1, a buffer layer 3 is formed on a semi-insulating gallium arsenide (GaAs) substrate 2, a channel layer 4 composed of undoped indium gallium arsenide (InGaAs) is formed on the buffer layer 3, and a barrier layer 5 is formed on the channel layer 4. The barrier layer 5 in FIG. 1 is a bi-layer structure composed of an n-type aluminum gallium arsenide (AlGaAs) layer (an electron-supplying layer) 5a and an undoped AlGaAs layer 5b. However, the barrier layer 5 may be a multi-layered structure composed of, for example, an undoped AlGaAs layer, an n-type AlGaAs layer, and an undoped AlGaAs layer, or it may only be an n-type AlGaAs layer. On the barrier layer 5, in order to form good ohmic contacts with a source electrode 8 and a drain electrode 9, a contact layer 6 composed of n-type GaAs is formed. On the upper surface of the contact layer 6, the drain electrode 9 and the source electrode 8 are formed and are brought into ohmic contact with the contact layer 6 by heat treatment.
Between the source electrode 8 and the drain electrode 9, the contact layer 6 is etched to form a recess therein so as to expose the barrier layer 5. The recess is formed by selectively removing the contact layer 6 by etching using an etchant that does not etch AlGaAs but etches GaAs, and by terminating the etching at the barrier layer 5 composed of AlGaAs. A gate electrode 10 is formed on the upper surface of the barrier layer 5 exposed from the contact layer 6 in a recess 7 and is in Schottky contact with the barrier layer 5. In addition, the surface of the HEMT 1 is covered with a protective layer 11 composed of SiN (silicon nitride).
In the HEMT structure described above, electrons in the n-type barrier layer 5 move over the heterojunction between the AlGaAs and the InGaAs to the channel layer 4 side that is lower in terms of energy. The electrons (two-dimensional electron gas) thus supplied from the barrier layer 5 to the highly purified channel layer 4 can drift without being scattered by donors in the barrier layer 5, so that the electrons have high mobility. That is, the channel layer 4 functions as a channel in which electrons flow, and the barrier layer 5 functions as a supplying source for supplying electrons to the channel layer 4, whereby, when a potential difference is applied between the source electrode 8 and the drain electrode 9, a drain current flows in the channel layer 4.
FIG. 2 is a schematic cross-sectional view showing a laminated structure of a conventional DMT. In a DMT 21 as shown in the figure, a buffer layer 23 is formed on a GaAs substrate 22, a channel layer 24 composed of n-type InGaAs is formed on the buffer layer 23, and a barrier layer 25 is formed on the channel layer 24. The barrier layer 25 in the DMT structure is formed of an undoped AlGaAs layer. On the barrier layer 25, in order to form good ohmic contacts with a drain electrode 29 and a source electrode 28, a contact layer 26 composed of n-type GaAs is formed. On the upper surface of the contact layer 26, the drain electrode 29 and the source electrode 28 are formed and are brought into ohmic contact with the contact layer 26 by heat treatment.
Between the source electrode 28 and the drain electrode 29, the contact layer 26 is selectively etched to form a recess therein so as to expose the barrier layer 25. A gate electrode 30 is formed on the upper surface of the barrier layer 25 exposed from the contact layer 26 in a recess 27 and is in Schottky contact with the barrier layer 25. In addition, the surface of the DMT 21 is covered with a protective layer 31 composed of SiN.
In the DMT structure described above, in the state in which a voltage is not applied to the gate electrode 30, electrons are stored in the n-type channel layer 24, and when a potential difference is applied between the source electrode 28 and the drain electrode 29 in this state, electrons as carriers move from the source electrode 28 to the drain electrode 29, so that a drain current flows.
In the HEMT 1 as described above, at the junction face between the channel layer 4 and the barrier layer 5, the combination thereof is an undoped layer and an n-type layer, respectively, and at the junction face between the contact layer 6 and the barrier layer 5, the combination thereof is an n-type layer and an undoped layer, respectively, so that each junction face has an aniso-type heterojunction. In addition, in the DMT 21 described above, at the junction face between the channel layer 24 and the barrier layer 25, the channel layer 24 is an n-type layer and the barrier layer 25 is an undoped layer, and at the junction face between the contact layer 26 and the barrier layer 25, the contact layer 26 is an n-type layer and the barrier layer 25 is an undoped layer, so that each junction face has an aniso-type heterojunction. As described above, in the conventional heterojunction FET, at least one of the junction faces between the channel layer and the barrier layer and between the barrier layer and the contact layer has an aniso-type heterojunction.
An aniso-type heterojunction is a junction formed of semiconductors having conduction types different from each other, or a junction formed of materials having electrical conductances significantly different from each other. For example, a junction formed of an n-type semiconductor and a p-type semiconductor, a junction formed of an n-type semiconductor and an undoped semiconductor, a junction formed of a p-type semiconductor and an undoped semiconductor, and a junction formed of a heavily doped layer (n+, p+) and a lightly doped layer (n−, p−) may be mentioned. In this connection, a heterojunction is a junction formed of materials having physical characteristics different from each other, for example, electron affinity and band-gap. In addition, heterojunctions other than aniso-type heterojunctions are called iso-type heterojunctions.
FIGS. 3A and 3B each show the energy band structure of the conduction band in the vicinity of the aniso-type heterojunction in the thermal equilibrium. FIG. 3A shows the energy level at the heterojunction face formed of an n-type GaAs layer 36 (or n-type InGaAs) and an undoped AlGaAs layer 37. In addition, FIG. 3B shows the energy level at the heterojunction face formed of undoped GaAs 38 (or undoped InGaAs) and an n-type AlGaAs layer 39, in which the conduction types in the top layer and the bottom layer in FIG. 3A are reversed.
When the heterojunction between a barrier layer and a semiconductor layer in contact therewith is an aniso-type conduction type pair, the bottom of the conduction band is localized at one side of the Fermi level EF, and the distribution of the depletion layer is also localized at the undoped layer side. For example, in the example shown in FIG. 3A, that is, when the aniso-type heterojunction formed of the n-type GaAs layer 36 (or n-type InGaAs) and the undoped AlGaAs layer 37 is considered, since the undoped layer is composed of AlGaAs having a smaller electron-affinity, the barrier height HB (energy barrier above the Fermi level EF)
formed at the heterojunction face is higher, so that the resistance through the heterojunction is increased. In addition, as shown in FIG. 3B, when the undoped layer is composed of GaAs (or undoped InGaAs) having a smaller electron-affinity similar to that in the n-type AlGaAs layer 39/the undoped GaAs layer 38 (or undoped InGaAs), the width Wv of the depletion layer formed at the n-type AlGaAs layer 39 side is increased, and also in this case, the resistance through the heterojunction is increased.
Consequently, in the aniso-type junction between the contact layer 6 (n-type GaAs) and the barrier layer 5 (undoped AlGaAs) in the HEMT 1 having a conventional structure, the barrier height at the barrier layer side is increased (see FIG. 3A). In addition, in the aniso-type junction between the barrier layer 5 (n-type AlGaAs) and the channel layer 4 (undoped InGaAs) in the conventional HEMT 1, the resistance in the undoped channel layer is increased while the width of the depletion layer generated in the barrier layer is increased (see FIG. 3B). Accordingly, the series resistance between the source and drain regions and the channel region under the gate electrode is increased.
On the other hand, in the conventional DMT 21, in the aniso-type junction between the contact layer 26 (n-type GaAs) and the barrier layer 25 (undoped AlGaAs) and also in the aniso-type junction between the channel layer 24 (n-type InGaAs) and the barrier layer 25 (undoped AlGaAs), since the barrier layer 25 is an undoped layer, band gap differences in the conduction band are almost distributed above the Fermi level and the barrier height is increased (see FIG. 3A), resulting in an increase in the series resistance which greater than that in the HEMT structure.
When the barrier height in the thermal equilibrium is high, the amount of increase and decrease in the barrier height is larger when the applied voltage is increased and decreased, and as a result, there is problems in that phenomena such as a drain current kink (see FIG. 6A) are generated, in which a drain current is abruptly increased at a certain voltage.